Low Power Sigma-Delta Modulator with Dynamic Biasing for Speech CODECs

In this paper the design of a low power sigma-delta modulator with dynamic biasing is presented. This design uses simple analog and digital components to achieve the low power purpose. In order to get a 12-bit resolution over the 4-kHz signal bandwidth for voice band applications such as PCM CODECs, an optimum choice is the second order modulator with an oversampling ratio of 128 and sampling frequency of 1.024MHz. To achieve low power, the dynamic biasing technique is used in our design. To implement the SDM, the modulator has been designed with fully differential switched capacitor integrator by the TSMC 0.35-um 2P4M CMOS process. The sigma-delta modulator achieves a 80-dB dynamic range, and the power consumption is only 1.4mW by a single 3.3-V supply.